void nRF24L01_Config(void)

{

  //initial io

CE=0;   // chip enable

CSN=1;   // Spi disable

SCK=0;   // Spi clock line init high

CE=0;

SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f);  // Set PWR_UP bit, enable CRC(2 bytes) & Prim:RX.   // RX_DR enabled..

SPI_RW_Reg(WRITE_REG + EN_AA, 0x01);

SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01);   // Enable Pipe0

SPI_RW_Reg(WRITE_REG + SETUP_AW, 0x02);  // Setup address width=5 bytes

SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x1a);   // 500us + 86us, 10 retrans...

SPI_RW_Reg(WRITE_REG + RF_CH, 0);

SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07);  // TX_PWR:0dBm, Datarate:1Mbps, LNA:HCURR

SPI_RW_Reg(WRITE_REG + RX_PW_P0, RX_PLOAD_WIDTH);

SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH);

SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); CE=1;

}

void nRF24L01_TxPacket(unsigned char * tx_buf)

{

CE=0;

SPI_Write_Buf(WR_TX_PLOAD, tx_buf, TX_PLOAD_WIDTH);    // Writes data to TX payload

SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e);   // Set PWR_UP bit, enable CRC(2 bytes) &

  // Prim:TX. MAX_RT & TX_DS enabled..

CE=1;

dalay10us();

CE=0;

}

unsigned char nRF24L01_RxPacket(unsigned char* rx_buf)

{

unsigned char revale=0;

  // set in RX mode

SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f);   // Set PWR_UP bit, enable CRC(2 bytes) & Prim:RX. RX_DR enabled..

CE = 1;   // Set CE pin high to enable RX device

dalay130us();

sta=SPI_Read(STATUS);   // read register STATUS's value

if(RX_DR) {  // if receive data ready (RX_DR) interrupt

   CE = 0;   // stand by mode

   SPI_Read_Buf(RD_RX_PLOAD,rx_buf,TX_PLOAD_WIDTH);  // read receive payload from RX_FIFO buffer

   revale =1;

}

SPI_RW_Reg(WRITE_REG+STATUS,sta);  // clear RX_DR or TX_DS or MAX_RT interrupt flag

return revale;

} 

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